Installing LiteX and Testing VexRiscv SoC

Before installing the LiteX framework, you should enter a Python virtual environment to prevent potential package conflicts when installing LiteX dependencies. The make cpu command will check whether LiteX is installed.

Adding Commands to Makefile for VexRiscv SoC Testing

Two commands added to the Makefile to test the VexRiscv SoC

• make cpu:
  This command checks if the LiteX toolchain is installed, then synthesizes the SoC and flashes the SoC design to the board. For SoC settings, please refer to: CPU.mk#L1-L6

• make cpu-test:
  This command compiles the code in cpu/bare-program to test the CPU. It prints messages via UART. The litex_term tool requires specifying the host port. The default port setting in the Makefile is /dev/ttyUSB0. To specify the port connected to your development board, run the command. litex_term used to load the binary program to the board and monitor the messages from UART.

  PORT=YOURPORT make cpu-test